The HP 1630 series of logic analyzers consists of 3 models designed to meet the needs of digital design and test engineers. The A & D model differ only in channel width - the HP1630A has 35 channels - and the HP 1630D has 43 channels. The HP 1630G has 65 channels, and additional system performance features for time tagging, time-positional charting, and module linkage histograms.
State listings and waveforms provide displays and windowing of address, data, status and control line activity. Selectable display modes include binary octal, decimal, hexadecimal, ASCII, relocation, user-defined mnemonics and microprocessor specific mnemonics. You can assign labels and display and/or trigger on code in terms of re-locatable or absolute addresses or mnemonics.
- 25 MHz speed
- Up to 65 channels (HP1630G)
- 1K memory
- Three clocks
- Demultiplexing
- Full compare mode
HP 1630A: For Eight-Bit Analysis
With its 35 channels, the HP 1630A is an economical solution for designs involving eight-bit microprocessors, most of which require 24 channels for address and data.
The HP 1630A provides a cost-effective solution and uncompromised measurement performance. In addition to state and timing analysis, the HP 1630A also offers system performance analysis with complete time-interval histrogramming, glitch triggering and capture and post-processing.
Most state analyzers offer many levels of triggering, and require you to string the levels together to trigger on the precise term of interest. The HP1630A provides four powerful resource terms (a, b, c, d) plus the ?‚ of each term, and NO STATE and ALL STATES triggering. You may assign an address, data or status value to any combination of resource terms. Each time the HP 1630A captures a bus transaction, it automatically tests to see whether that term is to be stored, and whether it is a trigger point or a restart term. Therefore, the HP 1630A accomplishes in one level what most other analyzers require three or more levels to accomplish.
